1. Field of the Invention
The invention generally relates to circuits, and in particular, to electrostatic discharge protection for circuits. Embodiments of the invention apply to all fields using CMOS processes (including BICMOS where CMOS ESD clamps are used).
2. Description of the Related Art
Electrostatic Discharge (ESD) is a major source of reliability failures in integrated circuits (ICs). For example, ESD arises when electrostatic charge accumulated on an object, for example a human body or a piece of equipment, is conducted onto another object, for example, a circuit board. This conduction of charge often results in damage to ICs, whether through electrical over-voltage stress or through thermal stress caused by large currents.
While it is possible to reduce the severity of an ESD event by reducing the build up of electrostatic charge potential, by, for example, controlling humidity in lab environments, the potential is difficult to completely mitigate. As a result, ICs incorporate ESD protection structures, allowing them to tolerate a certain level of ESD in order not to create reliability hazards. How an integrated circuit is assembled along with how the ESD protection structures are assembled is often referred to as an ESD protection strategy.
A representative ESD protection strategy, illustrating the protection of a device incorporating a single input/output (I/O) bond site and a single power and ground rail, is shown in FIG. 1. Three bond sites, one for the positive power supply VDD, one for the negative power supply VSS, and one for a signal labeled Signal are drawn at the left. Signal is protected to both VDD and VSS by primary clamp structures. A series resistor RESD and secondary positive and negative clamps further reduce the voltage applied as input to the I/O circuitry. The I/O circuitry is operatively coupled to the device core circuitry. A power clamp is placed between the VDD and VSS rails. Not all ESD protection strategies will include all of these components, and more complex strategies involving multiple positive and/or negative supply rails can include even more components. However the schematic of FIG. 1 illustrates the major components of an ESD protection strategy.
The various clamps of the circuit in FIG. 1 shunt the ESD current away from the I/O circuitry and the core circuitry, providing a low-impedance path through the device, thereby avoiding over-voltage stress on the I/O and core circuitry. In addition, the clamps themselves should be able to handle the ESD current without damage from thermal over-stress caused by large ESD currents.
However, including the ESD protection strategy into an IC comes at a significant cost, both in area (cost) and in performance (speed and signal integrity). Because the various clamps are often physically large, the ESD protection strategy can be a significant fraction of the total area for an integrated circuit. Therefore, the cost of the integrated circuit is directly impacted by the requirement for ESD tolerance. Additionally, because the clamps are physically large, they can exhibit significant parasitic capacitances, which act to reduce the speed at which a signal can be driven. This parasitic capacitance also can cause signal integrity issues on signal traces due to increased reflections. Accordingly, it is desirable to reduce the size of an ESD clamp.
In CMOS circuitry, four main structures are commonly used for constructing ESD clamps. These structures are (1) Diodes; (2) “Big FET” MOS devices; (3) “Snapback” MOS devices; and (4) Silicon Controlled Rectifiers (SCRs).
The simplest structure is the diode. A diode is commonly fabricated as a simple P-N junction (for example, a p-type diffusion region in an n-well or an n-type diffusion region in a p-well). As used herein, a well is a lightly doped region and a diffusion region is a heavily doped region. A diode structure is simple, has a very high current carrying capacity per unit area, and is easy to simulate. In many respects, the diode is close to an ideal clamp, but usually only in one direction (the other direction can also clamp depending on the type of diode—for example a Zener diode can clamp in both directions, but this is not commonly used in a CMOS process). As a result, most realizable ESD protection strategies that use diodes also use one or more of the other structures.
A structure using MOS devices for ESD clamps, known as the “Big FET” approach, uses a trigger circuit to turn on a relatively large MOS device (MOSFET) to conduct current during the ESD event. This approach is particularly attractive from a simulation perspective because no parasitic devices are involved, so that a Big FET ESD Clamp can be readily simulated in a standard SPICE-compatible simulator. However, a MOS device is a surface conduction device (unlike the bulk conduction of the snapback and SCR devices) and its current carrying capacity is relatively small per unit area. Because of this, the area used by a Big FET structure is often significantly larger than that used for either the snapback or SCR structures.
Another approach for ESD clamping with MOS devices uses what is called the “snapback” device. This approach makes use of the parasitic lateral NPN bipolar device that is inherent to an NMOS device. During an ESD event, the parasitic NPN bipolar transistor turns on, conducting the ESD current. This bulk conduction permits a snapback device to conduct more current per unit area than a surface-conduction device, such as used with the Big FET approach. The use of a snapback device is also attractive because the snapback device can be made self-triggering and can also be used as the output device for standard CMOS I/O structures, thereby making so-called “self-protecting” I/O's. However, the snapback device has a weakness: the parasitic bipolar transistor has significant variation from device to device within a multi-finger structure, and also across the width of a single finger. These variations mean that current is typically not equally distributed across the device. Furthermore, these types of devices have a tendency to become more conductive the hotter they get, which means that unless steps are taken to prevent it, the hotter spots in the clamp will conduct relatively more ESD current, which can cause a localized failure in the clamp. In order to prevent this, a current ballast structure can be inserted into the drain of the NMOS device to ensure even spreading of the ESD current. This ballast structure can increase the size and cost of the snapback device.
Another structure commonly used for ESD clamps is a Silicon-Controlled Rectifier (SCR). The SCR makes use of two parasitic bipolar transistors, an NPN and a PNP, and as a result it too has relatively large current conduction ability, potentially higher than snapback devices. However, unlike the snapback device, the self-triggering voltage for a typical SCR is typically in the 10-20V range, which is too high for the majority of applications in fine-geometry ICs. In order to overcome this limitation, SCRs use a trigger circuit to turn on during the ESD event, which complicates the design significantly. In addition, SCRs normally require more simulation and testing than snapback devices, which also complicates their use.
As a result of all this, the most common structure (after the diode) used in the industry is the snapback device. The remainder of this disclosure will focus on techniques to reduce the area used by the current spreading ballast associated with this device, which reduces the IC cost and potentially increases its performance.
The snapback device commonly used in ESD protection schemes is the parasitic NPN bipolar device that is inherent to all NMOS devices, as is shown in FIG. 2. The base of the NPN transistor is also the bulk of the NMOS device, while the emitter and collector of the NPN are the drain and source of the NMOS device, respectively.
FIGS. 3A and 3B illustrates a layout and cross sectional view of a single-finger snapback device 309 in a P-type substrate 305 complementary MOS (CMOS) technology with Shallow Trench Isolation (STI). N-type diffusion regions form a drain 301 and a source 302 for the NMOS device, while poly-silicon (also called “poly”) forms a gate 303. A P-type diffusion forms the bulk tap 304, allowing connection to the P-type substrate 305. Metallic contacts 306, 307, and 308 connect to the Drain, Source, and Bulk diffusion regions, allowing connection to the rest of the circuit. The parasitic NPN transistor of the snapback device 309 is a bulk device formed from the drain 301, the bulk and the source 302 of the NMOS device, while the parasitic resistance 310 connects the base of the NPN device to the bulk tap 304.
An idealized I-V curve of a snapback device 309 of an NMOS transistor is shown in FIG. 4. During an ESD event, current into the snapback device 309 suddenly increases the voltage at the drain 301. This causes avalanche multiplication of current across the Drain/Bulk junction, which causes current to be injected into the substrate 305. This current in turn builds up a voltage across the parasitic resistance 310 until the Bulk/Source junction becomes forward-biased, turning on the parasitic NPN transistor of the snapback device 309. This happens at a voltage and current given by VT1 and IT1, known as the snapback trigger point. After the NPN transistor of the snapback device 309 turns on, the voltage across the device drops to VH, known as the “Hold Voltage” while current flows from the drain 301 to the source 302 via the NPN transistor of the snapback device 309. The avalanche multiplication current continues to flow, maintaining the snapback. As the current continues to increase, the voltage across the NPN transistor of the snapback device 309 increases according to the device on resistance, RON. Unless otherwise limited, the power dissipation within the device can reach a point (VT2, IT2) where the heat generated by the ESD current causes thermal breakdown, which is also known as second breakdown. At this point, the device reaches its thermal limits, and undergoes destructive breakdown.
The various points in FIG. 4 are highly dependent upon several factors, including edge rate of the ESD event, dopant densities, physical dimensions, the circuitry connected to the gate 303, and the parasitic resistance 310.
Parameters of interest in the snapback I-V curve are the snapback trigger voltage VT1 and the second breakdown current IT2. VT1 is the maximum voltage that the circuit being protected should experience, while IT2 determines the ESD current protection limit.
ESD testing can be performed according to any of many discharge models, selected to model common ESD events. Models include the Human Body Model (HBM), the Charged Device Model (CDM), the Machine Model (MM), as well as some other application-specific models. Each model includes a high voltage source (typically measured in hundreds or thousands of volts) together with a discharge network that sets the shape and edge rate of the ESD current pulse. Different ESD models have different peak currents for a given ESD voltage. For example, a 2 kilovolts (kV) HBM discharge gives approximately 1.33 amps (A) of peak current, while 500 volts (V) CDM can give up to 2 amps (A) peak current (dependent on package size and type).
So long as the peak ESD current is less than the second breakdown current IT2, the snapback device 309 should be robust and remain undamaged from an ESD event. In order to reduce the size of the snapback device 309, the scaling of the second breakdown current IT2 with device width should be considered. Depending upon the specific characteristics of the snapback device and processing, the second breakdown current IT2 values are normally in the 3 mA/μm to 8 mA/μm range. For example, for a 2 A peak ESD current, the width of the ESD protection device should be in the 250 to 670 micron range. However, this width is applicable for ESD protection when the entire device is conducting simultaneously, i.e., evenly.
In practical snapback ESD protection devices, there are significant variations across the width of a single-finger NMOS device. This can be modeled by segmenting the snapback device 309 into a number of smaller devices in parallel, as shown in FIG. 5. In FIG. 5, the snapback device 309 has been modeled as a number of smaller devices 501, together with drain parasitic resistances 502 and source parasitic resistances 503.
Because of both random and systematic mismatches between the individual snapback devices 501 and the parasitic resistances 502 and 503, one of the devices of the model will snap back before the others. In a single-finger snapback device, this corresponds to snapback happening on only a small portion of the device. Because of the positive feedback nature of the snapback operation, this first region to enter snapback will tend to conduct the majority of the ESD current at that point. As the current continues to grow, this first region will tend to continue to take the majority of the ESD current, holding the drain/source voltage low, which will tend to prevent the rest of the device from entering snapback. This contributes to localized current crowding and reduces the effective width of the snapback device, decreasing the overall second breakdown current IT2 of the structure and increasing the likelihood of an ESD failure.
The parasitic resistances 502 and 503 act in a negative feedback manner to limit the current that each snapback device (or region thereof) will conduct. Each device (or region) 501 that undergoes snapback increases the current flow through its parasitic resistances 502 and 503. The drain parasitic resistances 502 increase the voltage on the common drain node above VH, thereby increasing the likelihood that other devices will undergo avalanche multiplication, triggering snapback, thereby providing additional low-impedance paths for the ESD current. This negative feedback effect only helps over a limited area, based on the values of resistances, the amount of diode leakage that gets multiplied (avalanche multiplication), and local die temperature. Typically, the more compact the ESD structure, the better the current distribution due to the ballasting resistances 502, 503. There are many ways to implement these ballasting resistances 502, 503.
For example, in FIG. 6, which illustrates a conventional two-finger snapback device, the parasitic ballasting resistances 502, 503 are implemented by a diffusion area between the contacts 601, 602 for the drain and/or source and the poly gate 603. Approximate values for the two ballasting resistors are expressed in Equations 1 and 2.
                              R          ⁢                                          ⁢          1                ≈                              Rcon            eff                    +                                    D              W                        *                          ρ              diff                                                          Equation        ⁢                                  ⁢        1                                          R          ⁢                                          ⁢          2                ≈                              Rcon            eff                    +                                    A              W                        *                          ρ              diff                                                          Equation        ⁢                                  ⁢        2            
In Equations 1 and 2, ρdiff is the sheet resistance of the diffusion region 600 and Rconeff is the contact resistance divided by the number of contacts in the drain (for Equation 1) or the source (for Equation 2). Sheet resistance is often written Rs. Usually, resistance R1 is much bigger than resistance R2 and is typically connected to the pad for providing ESD protection. The values of A, B, D, L and W can be varied to control the amount of current that the snapback device can safely handle while still taking manufacturing design rules into account. For example: A is typically made to be 1.5 times the minimum contact to gate spacing design rule of the process; L is typically between 1 to 1.2 times the minimum poly gate length for the MOS device; W is typically between 20 and 200 μm; B typically is 2 times the minimum diffusion overlap of contact; and D is made such that the resistance value is large enough to spread the current relatively evenly through the device.
The style of ballasting described in connection with FIG. 6 works on non-salisided diffusion regions, i.e., a diffusion that has values of sheet resistance ρdiff typically over 100 Ω/square, whereas salisided diffusions typically have sheet resistance ρdiff under 10 Ω/square), otherwise the size of D would become fairly large, and a corresponding transistor would be relatively large.
In FIG. 7, which illustrates a two-finger snapback device, the parasitic drain ballasting resistances (R1) are implemented by the diffusion area 700 between the drain contacts 701 and the non-salisided diffusion region 704 in the area between the drain contacts 701 and the poly gate 703. The parasitic source ballasting resistances (R2) are similar to those described earlier in connection with FIG. 6 (implemented by a diffusion area between the contacts 702 and the poly gate 703). Values for the two ballasting resistances are expressed in Equations 3, 4, and 5.
                              C          >          0                ;                              R            ⁢                                                  ⁢            1                    ≈                                    Rcon              eff                        +                                          D                W                            *                              ρ                                  ex                  -                  diff                                                      +                                          C                W                            *                              ρ                diff                                                                        Equation        ⁢                                  ⁢        3                                          C          ≤          0                ;                              R            ⁢                                                  ⁢            1                    ≈                                    Rcon              eff                        +                                          D                W                            *                              ρ                                  ex                  -                  diff                                                                                        Equation        ⁢                                  ⁢        4                                          R          ⁢                                          ⁢          2                ≈                              Rcon            eff                    +                                    A              W                        *                          ρ              diff                                                          Equation        ⁢                                  ⁢        5            
In Equations 3, 4, and 5, ρdiff is the sheet resistance of the diffusion region 700, ρex-diff is the sheet resistance of the non-salisided diffusion region 704 and Rconeff is the contact resistance divided by the number of contacts in the drain (for Equation 3 or Equation 4) or the source (for Equation 5). Usually resistance R1 is much bigger than resistance R2 and is typically connected to the pad for which ESD protection is to be provided. The values of A, B, C, D, L and W can be varied to control the amount of current that the snapback device can safely handle while still taking manufacturing design rules into account. It should be noted that some of the variable letters used for referencing dimensions are reused in other figures and correspond to other dimensions. A is typically made to be greater than or equal to about 1.5 times the minimum contact to gate spacing design rule of the process; L is typically between 1 and 1.2 times the minimum poly gate length for the MOS device; C can be the minimum design rule for the distance between poly and the salisided exclusion layer (it should be noted that in some processes this number can be negative or zero, that is the salisided exclusion mask can overlap or touch the poly hence Equation 3 simplifies to Equation 4); W is typically between 20 μm and 200 μm; E is typically the minimum separation for a contact to a salisided exclusion; the sum of B and G is greater than or equal to the minimum width for a salisided exclusion; B is typically greater than or equal to 2 times the minimum diffusion overlap of a contact; and D is made such that the resistance value is large enough to spread the current relatively evenly through the device.
The style of ballasting described in connection with FIG. 7 can be used with devices that have salisided diffusion regions to reduce the physical size of the ballasting resistor, which reduces the cost of the corresponding integrated circuit.
FIG. 8 illustrates the use of resistors for providing ballasting resistance for a conventional two-finger snapback device. As will be described later, the principles and advantages of these resistors can also be applied with embodiments of the invention. The ballasting resistances for the circuit illustrated in FIG. 8 are more complicated than those described earlier in connection with FIG. 7.
FIG. 9 is a schematic of a more detailed model for an equivalent circuit for a snapback device that will be used to describe the conventional circuit of FIG. 8, as well as the embodiments of FIGS. 10-13. For the snapback device illustrated in FIG. 8, the ballasting resistances R1, R12, R2, and R22 modeled in FIG. 9 includes resistances such as the resistance of a resistor 805, a resistance of the diffusion area between the drain contacts 801 and the poly gate 803, and a resistance between the source contacts 802 and the poly gate 803. As illustrated in FIGS. 8 and 9, the “drain” for the device is connected to the drain contacts 801 via the resistors 805. The resistance values for the ballasting resistances and for parallel resistances are expressed in Equations 6-13.each R1≈RR+Rcon  Equation 6
                              each          ⁢                                          ⁢          R          ⁢                                          ⁢          11                ≈                              F                          G              +              H                                *                      ρ            diff                                              Equation        ⁢                                  ⁢        7                                          each          ⁢                                          ⁢          R          ⁢                                          ⁢          12                ≈                              B                          2              *              F                                *                      ρ            diff                                              Equation        ⁢                                  ⁢        8                                          each          ⁢                                          ⁢          R          ⁢                                          ⁢          13                ≈                              F                          2              *              B                                *                      ρ            diff                                              Equation        ⁢                                  ⁢        9            each R2≈Rcon  Equation 10
                              each          ⁢                                          ⁢          R          ⁢                                          ⁢          21                ≈                              F                          G              +              H                                *                      ρ            diff                                              Equation        ⁢                                  ⁢        11                                          each          ⁢                                          ⁢          R          ⁢                                          ⁢          22                ≈                              A                          2              *              F                                *                      ρ            diff                                              Equation        ⁢                                  ⁢        12                                          each          ⁢                                          ⁢          R          ⁢                                          ⁢          23                ≈                              F                          2              *              A                                *                      ρ            diff                                              Equation        ⁢                                  ⁢        13            
In Equations 6-13, ρdiff is the sheet resistance of the diffusion region 800, RR is the resistance of a resistor 805, which can be implemented by a poly resistor as indicated in FIG. 8 or can another type of resistor such as a diffusion resistor, and Rcon is a single contact resistance. Usually R1 is much larger than R2, and typically, R1 is typically connected to the pad for providing ESD protection. The values of A, B, C, D, E, F, G, H, L and W can be varied to control the amount of current that the snapback device can safely handle while still taking manufacturing design rules into account. A and B are typically made to be greater than or equal to 1.5 times the minimum contact to gate spacing design rule of the process; L is typically between 1 and 1.2 times the minimum poly gate length for the MOS device; W typically is between 20 μm and 200 μm; E typically is greater than or equal to 2 times the minimum diffusion overlap for a contact; F is the contact to contact spacing, which is usually defined by the spacing of the real resistor 805; H is the contact width, which is usually a value defined by the process; G is typically equal to the minimum diffusion overlap for a contact; C and D set the RR resistance, which is made such that the resistance value is large enough to spread the current relatively evenly through the device.
The style of ballasting described in connection with FIG. 8 reduces the overall size of the snapback device as compared to the ballasting described earlier in connection with FIG. 7.